Simulation Methodology to Estimate Digital Substrate Noise Generation and Coupling to the Analog Section of Mixed Signal and RF Circuits

Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. To simulate this performance degradation, the total amount of substrate noise must be known. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator due to the long simulation times and high memory requirements. We are developing a methodology to simulate this substrate noise generation at a higher level taking noise coupling from switching gates into account and including noise coupling from the power supply. This paper describes a new simulation methodology to estimate noise coupling through common silicon substrate (high-ohmic) in mixed-signal circuits, while maintaining a large speedup with respect to SPICE simulations.