Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters
نویسندگان
چکیده
In this paper, we present a complete design methodology for high-performance low-power Analog-to-Digital Converters in deep submicron CMOS. This methodology is demonstrated on two ADC architectures, Flash and Folding&Interpolating(F&I). The designs were implemented in 0.18μm CMOS technology, achieving a high conversion rate of 2.6 GSamples/s for the Flash converter, and a 1 GSample/s rate for the Folding and Interpolating converter. In addition, the devices achieved a power consumption of 47 mW and 8mW respectively. Compared to previously published designs, this represents a 62.5% improvement in speed and 86% drop in power consumption for the Flash design and 3 times improved sensitivity (DNL) and 3.2 times reduction in power for the F&I design.
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