International Journal of Combined Research pISSN:2321-2241 Volume: 1; Issue: 7; November–2013

www.ijcrd.com Page 1 AbstractMultiplication is a fundamental arithmetic operation used in multimedia and DSP applications like convolution,filtering and compression. Since multipliers have a significant impact on the performance of the entire system, many high performance algorithms and architecture have been proposed to accelerate multiplication. Fixed-width booth multipliers provide high performance by reducing the number of partial products and reduces hardware complexity by removing adder cells from the least significant parts. There by huge truncation errors occurs. Thus area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best trade off solution among the both of them. In this project,a high speed fixed-width modified booth multiplier is proposed. Here we have first tried to design multipliers with different adders at the final stage and compare their speed and complexity of circuit i.e. the area occupied. While comparing the adders for designing a high speed fixed-width booth multiplier we found out that Carry Select Adders posses high speed which can be used as the final stage. Here we uses an adaptive compensation method which saves the establishment time of compensation circuit, provides varying column information and achieves high accuracy performance. The results are compared with conventional booth multipliers with different bits. Also a simple compensation circuit composed of simple logic gates is developed according to the proposed error compensation function.