Capacitance-voltage studies of atomic-layer-deposited MOS structrures on Gallium Arsenide and other III-V compound semiconductors Master of Science in Electrical and Computer Engineering P. Ye, Chair

Yang, Tian M.S.E.C.E, Purdue University, December, 2007. Capacitance-voltage studies of atomic-layer-deposited MOS structrures on Gallium Arsenide and other III-V compound semiconductors . Major Professor: Peide Ye. Si-based CMOS devices with traditional structure are approaching the fundamental physical limits. New device structures and materials must be explored to continue the trend of increasing electronic device speed and decreasing size at the same time. Recently, III-V compound semiconductors are considered as novel channel materials to replace Si due to their high electron mobilities. However, the main obstacle to implement III-V as novel channel materials for CMOS application is the lack of high-quality, thermodynamically stable insulators. Thus, systematic studies were carried out on atomic-layer-deposited (ALD) high-k dielectrics on GaAs and other III-V semiconductors. The experiment results show that interface quality strongly depends on surface pre-treatments, oxide materials and formation, post deposition annealing conditions, and also substrate semiconductors. A systematic interface study was also performed on ALD hafnium-aluminium-oxide laminate gate dielectric on GaAs. The results show that the hafnium-aluminium-oxide laminate structure gate dielectric improves the GaAs MOS characteristics such as dielectric constant, breakdown voltage and frequency dispersion. Due to small electron effective mass of GaAs, quantum capacitance effect is detrimental to the device performance. Indium tin oxide (ITO) gate was used to study quantum capacitance effect on GaAs. By using this transparent gate, strong inversion C-V is observed on GaAs MOS devices with ultra-thin dielectric layer. Capacitance value lowering was experimentally observed at electron accumulation.