Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic

The VLSI implementation of arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. Redundant arithmetic has received increasing interest in the past decade to reduce or eliminate carry propagation chains. The development of an analytical framework that expands the scope of functions that can be efficiently implemented using signed-binary representation is discussed in this paper. Implementation details are described that demonstrate the application of these results. Particular attention is placed on realizing the (a+b), –(a+b), (a–b), and –(a–b) functions in a complex ±1 multiplier serving as a pseudonoise code scrambler in wireless CDMA transceivers. *