A Fast-Settling, High Dynamic Range

In this project, we have designed a fully-differential operational transconductance amplifier with capacitive feedback network producing a close-loop gain of 0.2. The OTA was designed in the single-stage telescopic topology and simulation with HSPICE and achieved a very fast settling time of less than 5ns and a settling accuracy of at least 0.2%. The OTA has the differential output swing of ±1.8V and a dynamic range greater than 85dB while consuming 7.2mW from a 3V supply for the main amplifier and 1.9mW for the bias network. I. Design Approach and Decisions Choosing the right overall circuit topology for a given set of specifications so as to avoid over-designing the circuit is one of the most critical design decisions to start out with. We begin investigating the specifications of the project very closely, and look at the pool of candidates for the best circuit topology. For the single-stage design, we consider telescopic, folded-cascode and gain-boosting amplifiers. Two-stage design consists of using a full 2-stage or a preamp followed by a full-stage amplifier. However, the fact that we only need 0.2% settling accuracy tells us that the open-loop gain for the OTA need not be extremely high (as shown later in Section III). In fact, an open-loop gain of more or less 1000 at around the maximum differential swing should suffice. Hence, to employ the design in a two-stage or gain-boosting topology may give excessive dc gain while dissipate much more power. Supply VDD 3V Closed-loop gain, c 0.2 DR at output ≥ 85 dB Settling accuracy ≤ 0.2% Settling time, ts ≤ 5 ns Process EE240 0.35um Process corners slow/nominal/fast Table 1: Project specifications Dynamic range of 85dB indicates that the OTA should be designed with large output swing range and that the integrator will need a large load capacitor at the output. A full two-stage design is the best candidate in terms of the output differential range, but the major drawback is the need for a minimum of four current legs (all drawing comparable currents) and thus may have big impact on the power consumption. At this point we decided to forego the 2-stage design. In addition, a 5ns settling time is quite a stringent requirement and this makes the fast and simple single-stage telescopic or folded-cascode very attractive. The folded-cascode design suffers from the extra current leg introduced by the folded structure while only providing one extra Vds headroom advantage at the output swing. At this point, telescopic one-stage OTA is chosen as our design choice, with the gain-boosting topology in mind in case we need larger open-loop gain. However, after hand-analysis and repeated SPICE simulations, extra open-loop is not necessary and adding gain-boosting enhancement would be an over-design, add extra complexity and dissipate unnecessary power. Close-loop gain of less than unity leads to the bigger feedback facto, F and helps reduce the noise that is proportional to 1/F. However, a large step needed at the input will create longer time for slewing. With all of these issues in mind, we begin designing our onestage telescopic OTA. II. Circuit Schematics and Parameters Tabulation Here we have shown the final design of our complete schematics. Figure 2. Main amplifier schematic (I1, I2, and I3 will be generated by the bias network) Figure 3. Biasing circuitry Figure 4. CMFB circuit Table 2: Final device sizes and parameters W (um) L (um) gm (mS) Id (mA) Gm/Id (1/V) Vov (V) Main Amplifier M1 500 0.35 20.4 1.2 17 0.118 M2 500 0.35 20.4 1.2 17 0.118 M3 800 1 16.7 1.2 13.92 0.144 M4 800 1 16.7 1.2 13.92 0.144 M7 800 1 9.17 1.2 7.64 0.262 M8 800 1 9.17 1.2 7.64 0.262 M9 800 1 9.6 1.2 8 0.25 M10 800 1 9.6 1.2 8 0.25 CMFB Amplifier Mb1 500 (M=2) 0.35 37 2.4 15.42 0.130 Mc1 265 1 0.27 0.015 18 0.111 Mc2 265 1 0.27 0.015 18 0.111 Mc3 16.5 0.35 0.29 0.015 19.33 0.103 Mc4 16.5 0.35 0.29 0.015 19.33 0.103 PMOS Cascode Bias Mb5 80 1 0.92 0.12 7.67 0.261 Mb6 80 1 0.92 0.12 7.67 0.261 Mb7 20 1 0.31 0.12 2.58 0.774 Mb8 80 1 0.92 0.12 7.67 0.261 Main Bias Mbias1 35 0.35 1.92 0.12 16 0.125 Mbias2 35 0.35 1.92 0.12 16 0.125 Mbias3 35 0.35 1.92 0.12 16 0.125 Mbias4 35 0.35 1.92 0.12 16 0.125 Mbias5 80 1 0.98 0.12 8.17 0.245 Mbias6 80 1 0.98 0.12 8.17 0.245 Mbias7 3.75 1 0.34 0.12 2.83 0.706 Mbias8 3 0.35 1.9 0.12 15.83 0.126 Mbias9 3 0.35 1.9 0.12 15.83 0.126 Mbias10 3 0.35 1.9 0.12 15.83 0.126 Mbias11 3 0.35 1.9 0.12 15.83 0.126 Mbias12 20 1 0.24 0.03 8 0.25 Capacitor sizes CL 3pF Cf 4pF Cs 0.8pF Common-mode Voltages Vic = 0.8V (chosen such that MB1 that supplies tail-current has enough headroom) Voc = 1.5V III. Design Flow and Equations We start with static accuracy requirement. Since we use one-stage telescopic approach which does not provide very high open-loop gain, we decide to allocate a large portion of total settling error (80%) to the static finite-gain error.