“ A Verilog to C Compiler . ” RSP 2000
نویسنده
چکیده
This paper describes a compiler which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and also performs logic minimisation. Busses of up to 32 or 64 bits can be modelled as C integers whereas larger busses are automatically split. We describe the motivation, method and quality of the results.
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