Executing Sequential Binaries on aClustered

With the conventional superscalar approach of exploiting ILP from a single ow of control giving diminishing returns, integrating multiple processing units on a die seems to be a promising approach. However, in these architectures, the resources are partitioned such that a thread is allocated exclusively to a processor. This risks wasting resources when a thread stalls due to hazards. While simultaneous multithreading (SMT) addresses this problem with complete resource sharing, its centralized structure may impact the clock frequency. An intuitive solution is a hybrid of the two architectures, namely, a clustered SMT architecture, where the chip has several independent processing units, with each unit having the capability to perform simultaneous multithreading. In this paper, we describe a software-hardware approach that enables speculative execution of a sequential binary on a clustered SMT architecture. The software support includes a compiler that can identify threads from sequential binaries. The hardware includes support for inter-thread register synchronization and memory disambiguation. We evaluate the resulting clustered SMT architecture and show that it is more cost eeective than a centralized SMT and architectures where all the resources have a xed assignment.