High-Level Synthesis using Dependence Flow Graphs as the Intermediate Form
نویسنده
چکیده
This paper describes an ongoing high level synthesis project using dependence ow graphs as intermediate form. This HLS system takes a behavioral description written in a subset of VHDL and generates an RTL VHDL description that implements the design. We use dependence ow graphs as an intermediate form. We only describe the compilation part of the HLS system and dependence ow graphs.
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