Design of a NULL Convention Self-Timed Divider
نویسنده
چکیده
An unsigned 8-bit ÷ 4-bit delay-insensitive iterative divider is developed using the NULL Convention Logic paradigm. The divider is simulated using a 0.5μm CMOS process with static cells. The simulation of the initial design yielded an average cycle time of 75.92 ns with a transistor count of 4,721. A subsequent design increased throughput by 18%, while only increasing area by 2.7%.
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