AMDREL: On Designing Reconfigurable Embedded Structures for the Future Reconfigurable SoC for Wireless Communication Applications

The objective of the AMDREL (Architectures and Methodologies for Dynamic Reconfigurable Logic) project is to develop methodologies, tools and intellectual property blocks to be integrated in a partly dynamically reconfigurable System-on-Chip (SoC) implementation platform for the efficient realization of wireless communications systems. The proposed tools, reusable intellectual property blocks and the mixed granularity reconfigurable blocks will be used for the development of systems from the wireless communication domain including critical paths of wireless LAN systems (e.g. HIPERLAN/2, IEEE 802.11a). The developed blocks and tools will be integrated as a System-on-Chip. There are three types of reconfigurable hardware involved: i) coarse-grain reconfigurable hardware (i.e. multipliers with reconfigurable wordlength, radix etc.) with power dissipation being an important consideration, ii) fine-grain reconfigurable hardware (FPGA-like structures). Also, the tools for mapping logic to these reconfigurable blocks and iii) reconfigurable interconnect for the blocks mentioned above. AMDREL offers significant innovations in all the above areas of reconfigurable computing.