An experimental analysis of spot defects in SRAMs: realistic fault models and tests
نویسندگان
چکیده
In this paper a complete analysis of spot defects in industrial S R A M s will be presented. All possible defects are simulated, and the resulting electrical faults are transformed into functional fault models. The existence of the usually used theoretical memory fault models will be verified and new on,es will be presented. Finally, a new march test detecting all realistic faults, with a test length of 14n, will be introduced, and its fault coverage is compared with other known tests.
منابع مشابه
Technology and layout-related testing of static random-access memories
Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that ar...
متن کاملRealistic Static Linked Faults and Dynamic Faults in SRAMs
Memory testing commonly faces two issues: the characterization of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them. Among the different types of algorithms proposed for testing Static Random Access Memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. The continuous evolution of the memory technolog...
متن کامل[Proceeding] A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs
Among the different types of algorithms proposed to test Static Random Access Memories (SRAMs), March Tests have proven to be faster, simpler and regularly structured. A large number of March Tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of...
متن کاملAnalysis and Test Development for Parasitic Fails in Deep Sub-Micron Memory Devices
E merging technology trends are gravitating towards extremely high levels of integration at the package and chip levels, and use of deeply scaled technology in nanometer, approaching 10nm CMOS. Challenges will arise due to the ability to design complex systems such as robots that encompass sensors, transducers, communications systems and processors, all of which require memory devices, and are ...
متن کاملCombined Delay Fault Modeling and Simulation
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this problem a combined delay fault (CDF) model has been developed, which models delay faults caused by the combination of spot defects, parametric process variation, and capacitive coupling. The spot defects are modeled as...
متن کامل