Paper Title Low Cost and Low Power Floating-point Fused Multiply-Add Unit Design with Proxy Bits and Weighted 2-Level Booth Encoding

With the appearance of high performance mobile devices, low cost and low power consumption have become important issues in high performance processors. To meet the needs, low cost and low power floating-point fused multiply-add unit is proposed in this paper. According to the area and power consumption analysis, the multiplication part in fused multiplyadd operation accounted for most power consumption and area. Thus, the proposed floating-point fused multiply-add unit used a new weighted 2-level Booth encoding algorithm to optimize the multiplier. In additional, proxy bits, which can represent redundant bits, from the cancellation in subtraction operation is proposed. The aim of this paper was to be achieved by optimizing a shifter, leading zero anticipator, and adder using the proxy bits. The synthesis and power consumption analysis results show that the proposed floating-point fused multiply-add unit reduced area by 37.3%, and improves the latency by 10.8% compared to a conventional floating-point fused multiply-add unit under no clock constraints. In addition, the proposed floating-point fused multiply-add unit reduced area and power consumption compared to the conventional unit by 31.6% and 23.3%, respectively under 2.5ns timing constraints. Therefore, the proposed floating-point fused multiply-add unit will contribute to server and mobile purpose processors’ high performance, low power, and low cost requirements.. (Abstract) KeywordsFloating-point unit, Fused multiply-add unit, Low power, Low cost, Weighted 2-level Booth encoding, Proxy bits