Test Circuits for 3-D Systems Integration

Three test circuits have been developed to experimentally demonstrate and stress the state-of-the-art in 3D integrated systems. Several critical elements of this emerging technology, synchronization, power delivery, and thermal management, are just beginning to be explored. The three test circuits explore these three fundamental design issues. The first test circuit examines multi-plane synchronization for a stacked system of three device planes. Experimental data compare skew, slew, and power consumption for different network topologies. The second test circuit examines power delivery in a three plane 3-D system. The noise propagation characteristics within the power and ground networks are experimentally assessed by varying the through-silicon via (TSV) density and using dedicated planes. The third 3-D circuit includes five CMOS planes, two logic planes and three memory planes, and includes multiple circuits that examine a range of 3-D design issues. The test structures are designed to evaluate thermal coupling between CMOS device planes and decoupling capacitance in 3-D power delivery networks. These test circuits are discussed, and trends and challenges are outlined.