Current Status and Addressing the Challenges of Hf-based Gate Stack toward 45nm-LSTP Application
نویسندگان
چکیده
1. Introduction In spite of intensive efforts, still some serious items to be solved remain for high-k gate stack. By narrowing down the items, gate electrode has become one of the most problematic issues due to unavoidable Fermi level pinning [1]. In this talk, after a brief benchmarking of high-k gate stack technology, we lay particular stress on the impact on the electrical characteristics concerning the gate electrodes [poly Si and metal gate including fully-silicided(FUSI) gate] and interfacial reaction control [post deposition anneal(PDA) and nitride capping] as well as Hf-based high-k dielectric material.
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