Evolutionary MOSFET Structure and Channel Design for Nanoscale CMOS Technology by

The constant pace of CMOS technology scaling has enabled continuous improvement in integrated-circuit cost and functionality, generating a new paradigm shift towards mobile computing. However, as the MOSFET dimensions are scaled below 30nm, electrostatic integrity and device variability become harder to control, degrading circuit performance. In order to overcome these issues, device engineers have started transitioning from the conventional planar bulk MOSFET toward revolutionary thin-body transistor structures such as the FinFET or fully-depleted silicon-on-insulator (FDSOI) MOSFET. While these alternatives appear to be elegant solutions, they require increased process complexity and/or more expensive starting substrates, making development and manufacturing costs a concern. For certain applications (such as mobile electronics), cost is still an important factor, inhibiting the quick adoption of the FinFET and FDSOI MOSFET structures while providing an opportunity to extend the competitiveness of planar bulk-silicon CMOS. A segmented-channel MOSFET (SegFET) design, which combines the benefits of both planar bulk MOSFETs (i.e. lower process complexity and/or cost) and thin-body transistor structures (i.e. improved electrostatic integrity), can provide an evolutionary pathway to enable the continued scaling of planar bulk technology below 20nm. In this work, experimental results comparing SegFETs and planar MOSFETs show suppressed short-channel effects and comparable on-state current (despite halving the effective device width). In addition, three-dimensional device simulations were used to optimize and benchmark the bulk SegFET and FinFET designs. Compared to the FinFET design, the results indicate that the SegFET can achieve similar on-state current performance and intrinsic delay (for the same channel stripe pitch) at a lower height/width aspect ratio and less aggressive retrograde channel doping gradient for improved manufacturability, making it a promising candidate for continued bulk-silicon CMOS transistor scaling. High-mobility channels are also investigated in this work for their potential to improve MOSFET performance, but issues with physical material parameters (electrostatic control, strain 2 effects, etc.) and process integration necessitate careful design when implementing these materials in the MOSFET channel regions. Because germanium (Ge) and silicon-germanium (Si 1-x Ge x) alloys are Group IV materials like silicon (Si), and since these materials are already extensively used in mainstream volume integrated-circuit manufacturing, they represent the most straightforward path to integrating high-mobility channels on silicon. Device simulations are used to optimize Si 1-x Ge x channel thickness and Ge concentration for Si 1-x Ge x /Si heterostructure p-channel MOSFETs; it is found that a thin (< 5 nm) channel with moderate (20%-40%) Ge concentration is optimal …