Efficient VLSI Architecture for Variable Length Block LMS Adaptive Filter

In this paper, we made an analysis on computational complexity of block least mean square (BLMS) finite impulse response (FIR) filter and decompose the filter computation into M sub-filters, where M = N/L, N is the filter length and L is the block-size. Each sub-filter acts like a short-length BLMS FIR filter of size L. The proposed decomposition scheme favors timemultiplexing the filtering computation and weight-increment term computation of each short-length filter. Using the proposed scheme, we have derived an efficient architecture for BLMS FIR filter. The proposed structure can be reconfigured for different filter lengths with negligible overhead complexity and it supports variable convergence factor μ. Besides, the proposed structure has 100% hardware utilization efficiency (HUE) and its register complexity is independent of block-size. Compared with recently proposed LMS-based FIR structure, the proposed structure involves L times more multipliers, proportionately less adders and the same number of registers, and it offers L times higher throughput. Due to register and adder saving, the proposed structure has significantly less area-delay product (ADP) and energy-per sample (EPS) than the existing structure. ASIC synthesis results shows that the proposed structure for block-size 4 and filter length 64 involve 21.4% less ADP and 26.6% less EPS than those of the existing structure and offers 3.8 times higher throughput. Adaptive filters, Block Least Mean Square (BLMS), VLSI, Architecture.