Enhanced Concurrency Control with Transactional NACKs

Transactional memory (TM) is a promising technique that simplifies parallel programming by supporting atomic and isolated execution of code sections. To provide robust performance and fairness guarantees, however, TM must dynamically adjust the degree of concurrency among transactions. To design an efficient concurrency controller for TM, critical system information, such as dependencies among transactions and current utilization level of the system, should be provided in an accurate and inexpensive manner. However, efficiently obtaining such information is often the most challenging design problem. To address the issue, we have looked at hardware features that can be used to characterize transactional behavior. In particular, we identify NACKs, which are readily available in several TM designs to handle conflicts between transactions, as the mechanism to efficiently collect the transactional information of the system. In this paper, we propose three novel, efficient use cases of NACKs for TM systems to demonstrate the potentials of utilizing NACKs intelligently: 1) accurate deadlock detection, 2) dependency tree construction, and 3) carrier sensing. We also describe a prototype design that extends the baseline TM systems to support the proposed techniques. To evaluate the effectiveness of such approach, we use the proposed techniques to implement an enhanced concurrency controller that performs aggressive stalling, dependency chain cutting, and exponential backoff with overshoot avoidance. Our preliminary results demonstrate that the proposed techniques can significantly improve the performance of hardware and hybrid TM systems (up to 21.5%).