High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm

CORDIC (Coordinate Rotation Digital Computer) is a well known hardware algorithm for computing various elementary functions. In this work two 32 bit radix 4 CORDIC architectures, unfolded and folded are implemented on available FPGA. The unfolded pipelined architecture consists of a linear array of modules in each of which a micro rotation is carried out. The folded architecture uses pipelining and parallelism. The proposed architectures present a good tradeoff between latency and hardware complexity when compared to already existing CORDIC architectures. The folded architecture requires 25% of the resources as compared to unfolded architecture and operates at a frequency of 56.069MHz hence can be used for real time applications.