Testability Guided Hierarchical Test Generation with Decision Diagrams

A unified approach is presented for calculation multi-level testability measures and for testability guided hierarchical automated test pattern generation (ATPG) for digital systems. The methods and algorithms are based on path tracing procedures on decision diagrams. On the higher level the system is presented as a network of register transfer level (RTL) components, and on the lower level each RTL-component is represented as a network of macros (subcircuits) where to each macro a structurally synthesized BDD (SSBDD) corresponds. The higher level DD-model of the system is synthesized from the structural VHDL description, whereas the lower level SSBDD macros are synthesized from the gate-level netlist given in the EDIF format. Differently to traditional testability calculation and ATPG approaches, no libraries of network components are needed. Generic procedures have been developed for DDs representing either low or high-level components. The procedures initially developed for binary DDs were generalized for higher level DDs of RTL networks. The use of DDs makes the model generation very easy, and manipulation very efficient. Experimental results show the advantages of the new testability guided ATPG approach.