Fpga Design and Implementation of a Real-time Vision Based Lane Departure Warning System
نویسندگان
چکیده
Using a vision-based solution in intelligent vehicle application often requires large amounts of memory to handle the video stream and image process, which increases the complexity of the hardware and software. In this paper, we present a Field-programmable Gate Array (FPGA) implementation of a vision-based lane departure warning system. By taking video frames, the line gradient is estimated and the lane marks are found. By analyzing the position of the lane mark, the departure of the vehicle will be detected in time. This idea has been implemented in Xilinx Spartan6 FPGA. The lane departure warning system uses 39% logic resources and no memory of the device. The average availability is 92.5%. The frame rate is 30 frames per sec (fps).
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