Speeding up SAT Based ATPG for Logic Veri cation by Recursive Learning

Recursive Learning (RL) is a circuit-structure-based method for computing all necessary assignments. Recursive learning technique can be combined with diierent CAD algorithms and techniques in testing, veriication and optimization. In particular, it is used for Automatic test pattern generation(ATPG) which has been applied to many areas of logic synthesis and formal veriication including combinational veriication and logic minimization. Satissa-bility (SAT)-based-ATPG is one of the most eecient algorithms in testing. In this project, we investigate applying recursive learning to the SAT-based-ATPG. We then use the revised the SAT-based-ATPG for combinational logic veriication. The SAT-based-ATPG with global implication heuristics (iterated global implications) is very eecient and it does not seem to leave much room for improvement. However, our preliminary results show that adding recursive learning information does speed up the SAT-base-ATPG for combinational logic veriication.