A flexible tree-based platform for design space exploration of hierarchical FPGA architectures

For many years, research on FPGA-type programmable hardware architectures has focused mainly on optimising regular non-hierarchical architectures. In the exploration of their design space, some design parameters have a significant impact on the layout area, which is directly related to interconnect delay. An estimation of this impact can be derived from a prediction of the area of the basic FPGA building blocks. For non-hierarchical FPGA architectures, reliable area predictions are easily achieved. However, recent FPGAs are becoming ever more complex: the architectures are often hierarchical and contain embedded higher-level components. Here, a priori area estimation is much more complicated. In this paper, we present the development of a generic tree representation for hierarchical FPGA architecture layouts. This representation can be used to derive reliable area estimations. Integrated in a partial design flow, this provides a framework for the exploration of different architectural parameters as well as layout options. Keywords— hierarchical FPGA architectures, architecture modelling, design space exploration