VHDL Implementation for Adaptive FIR filter and its Novel Application using Systolic Architecture

The systolic architecture is an arrangement of processor where data flows synchronously across array element. To obtain perfect solution parallel computing is use in contradiction. The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. This paper demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language and Field Programmable Gate Arrays (FPGAs). The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used.