Interactive Learning ‘i’oci~lbox for Ilogic Synthesis with Vrdl

With the advance :in Computer-Aided Design technology, digital design in the scale of VLSI (Very Large Scale Integrated Circuit) has moved from bottom-up design approach to top-down design methodology with the aid of advanced Electronic Design Automation tool. The most common design platform is the tools that make use of VHDL (Very High Speed Integrated Circuit Hardware Descriptive Language) as design media. It has become the stamdard approach of designing digital circuit/system. However, mastering VHDL for design is not as simple as it seems that it is simply high level programming tot mimic the design hardware, even for experienced designer. An interactive learning tool with the capability of conducting experiments concurrently is proposed to enhance the teaching quality and provide amber training for students in learning VHDL.