Demystifying EPIC and IA-64: 1/26/98

Using a next-generation architecture technology that Intel and Hewlett-Packard call EPIC (explicitly parallel instruction computing), Merced and future EPIC processors threaten the performance lead held today by RISC processors. EPIC is not entirely new, borrowing many of its ideas from previous RISC and VLIW designs as well as from recent academic research. EPIC has an inherent performance advantage over existing architectures, however, because it is a synergistic assembly of the latest innovations into one architecture. To compete with EPIC processors from Intel, existing RISC architectures are likely to adopt a similar combination of EPIC features in their future versions. During last year’s Microprocessor Forum, Intel and HP gave a high-level, incomplete description of IA-64, for which the companies coined the generic name EPIC (see MPR 10/27/97, p. 1). Nevertheless, we know that EPIC provides a large number of addressable registers, eliminating the need for register renaming and reducing cache accesses. It also provides instruction dependency hints, simplifying instruction issue logic. EPIC uses predicated execution to eliminate some branches, thereby increasing scheduling freedom for the compiler, allowing parallel execution of both paths of branches, and reducing opportunities for misprediction. EPIC uses speculative loads to enable well-behaved accesses to memory as soon as the address can be computed, hiding memory latency. Intel and HP have revealed only a few details of EPIC and IA-64, but we can project more details than publicly disclosed by considering how these EPIC features can be applied to solve today’s performance bottlenecks. IA-64 may impose programming restrictions to accommodate clustering of execution units and registers, greatly simplifying hardware without unduly degrading the processor’s throughput. It may also use delayed branches to specify branch target addresses as early as possible, reducing reliance on accurate branch prediction. IA-64 may use load/ store instructions that also return the effective address as a result, reducing the overhead of hoisting speculative loads above earlier stores. At first glance, retrofitting these EPIC features onto an existing instruction set seems to require adding more bits, breaking binary compatibility with existing software. While a few new instructions can be added easily to an instruction set using unused opcodes, adding general-purpose registers and predicated execution seems more difficult, or even impossible, without breaking binary compatibility. For many RISC architectures, however, most—if not all—of the known EPIC features can be added without breaking compatibility. EPIC is a natural evolution of RISC: its fixed-length instruction formats and load/store instructions enable the EPIC features to be added easily.