Power Optimization for Simultaneous Scheduling and Partitioning with Multiple Voltages

This paper presents a synthesis scheme based on simulated annealing, to minimize power consumption with resources operating at multiple voltages under timing and resource constraints. The scheme considers both scheduling and partitioning simultaneously to reduce power consumption with considering layout issues. Experimental results with a number of DSP benchmarks show that the scheme can achieve significant power reduction at the expense of running time. Key-Words: low power, scheduling, partition, multiple voltages