Mitigation of Soft Errors on 65nm Combinational Logic Gates via Buffer Gate

Through technology development, VLSI fabrication is becoming smaller in size which causes much sensitivity of VLSI circuit to noise effects especially soft error. In this paper, we present a method to mitigate soft error in combinational logic gates based on 65 nm technology that is able to reduce the possibility of noise propagation in combinational logic gate. We evaluate our result based on ISCAS 85 benchmark circuit. Through DFS algorithm and using analytical model derived by stimulation of each combinational logic gate in transistor layer, soft error is processed in paths of ISCAS 85 circuit benchmark and a single buffer logic gate is added to the end of the paths that have more potential to be affected by soft error. Therefore, possibility of soft error distribution through circuit benchmark is measured. The buffer gates that mitigate soft errors on the benchmark paths are kept and others are eliminated. After processing, new circuit benchmark is available that includes added buffer logic gate to only critical paths. This is more reliable than initial ISCAS85 circuit benchmark in terms of illuminating soft error. The results show that possibility of soft error distribution is reduced intelligently and due to adding buffer gate to just suspicious paths of benchmark, power and delay are optimum.