Moment-based techniques for RLC clock tree construction

Multi-Chip Modules (MCM's) provide a medium for integration of several bare dies on a multi-layer substrate. MCM technology has gained popularity in recent years with the promise of orders of magnitude reduction in inter-chip delay and power dissipation over single chip packaging [2]. By virtue of a faster interconnect MCM's aim at alleviating, to a large extent, the bottleneck o ered by conventional packaging. However the interconnection medium of a typical MCM substrate is characterized by a signi cant inductance and routing distances of several centimeters. Accurate analysis of MCM interconnect requires the use of lossy transmission line models. In comparison, the on-chip interconnect design has been traditionally been performed by modeling lines as lumped resistance-capacitance (RC) networks. The need for new methods which take into account the requirements of the MCM scenario while being comparable in e ciency to traditional IC design techniques is of prime importance. This paper addresses the problem of designing the clocking network for an MCM. The design of the clock distribution network of an MCM is critical from the point of view of achieving desired system speed along with reliable operation. The clock distribution network on a MCM substrate can be considered to be a tree of lossy transmission-lines delivering the clock signal to the various dies placed on the substrate, with bu ers inserted into the