A Uni ed Systolic Array for Fast Computation of the DCT/DST/DHT

This paper proposes a two-dimensional (2-D) VLSI architecture using a uni ed systolic array for fast computation of the discrete cosine transform/discrete sine transform/discrete Hartley transform (DCT/DST/DHT). The N -point discrete transform is decomposed into evenand oddnumbered frequency samples and they are computed independently at the same time. The proposed uni ed systolic array architecture can compute the DCT, DST, and DHT by de ning di erent coe cient values speci c for each transform. Also, we present another architecture for computation of the DHT, a modi ed version of the uni ed systolic array structure, which is faster than the uni ed architecture by a factor of two. In addition, the proposed uni ed architecture can be employed for computation of the inverse DCT/inverse DST/inverse DHT (IDCT/IDST/IDHT) with some modi cations. Subject terms: DCT; DST; DHT; uni ed systolic array.