Performance and economy of a fault - tolerant multiprocessor

The FfMP (Fault-Tolerant Multiprocessor) is one of two central aircraft fault-tolerant architectures now in the prototype phase under NASA Langley Research Center sponsorship. 1,2 The intended application of the computer includes such critical real-time tasks as "fly-by-wire" active control and completely automatic Category III landings (zero visibility and zero ceiling) of commercial aircraft. The life-critical nature of these tasks and the profit-oriented attitude of airlines translate into some very challenging and sometimes contradictory computer requirements. For example, a candidate computer should be able to execute tasks on time, without significant delays, be extremely reliable, and yet be cost-effective. At a first glance these requirements seem to be in conflict with each other. After all, to meet the performance criteria some sort of parallelism such as multiprocessing capability would be in order. Second, to meet the reliability and safety requirements it would be necessary to use redundancy since no simplex computer could possibly meet the "extremely improbable" failure criterion of the Federal Aviation Administration. The result is a computer that could be very expensive. Yet it may still be cost-effective. The reason is that it is the balance between the benefits and costs that determines the cost-effectiveness of a product; cost alone is not a pertinent criterion. In this paper we intend to show that the FfMP architecture is a viable solution to the multi-faceted problems of safety, speed, and cost. The next section briefly describes the FTMP architecture. The third section is devoted to the performance analysis. Three job dispatch strategies are described, and their results with respect to job-starting delays are presented. The first strategy is a simple First-Come-First-Serve (FCFS) job dispatch executive. The results of FCFS were obtained by running a representative job-mix on a multiprocessor and through Markov modeling techniques. The other two schedulers are an adaptive FCFS and an interrupt driven scheduler. The results of these schedulers were obtained by a