Analysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop

Phase noise (PN) in phase locked loop (PLL) system is an important parameter in communication system. It degrades the system performance by increasing bit error rate (BER). The PLL concept was first appeared in the papers by Appleton in 1923 and de Bellescize in 1932 [1]. It is essentially a control system which employs feedback mechanism to synchronize the phase of output signal with the phase of a reference signal [2], [3]. When the PLL is in lock, there is a small phase difference between the two input signals of a phase frequency detector (PFD) and produce a dc voltage at the detector output, which is required to shift voltage controlled oscillator (VCO) from its free-running frequency and keep the loop in lock. A basic PLL consists of a VCO, a PFD and a loop filter (LF). In the modern PLL system a charge pump (CP) is included with the PFD unit. It produces a current proportional to the error between the reference and feedback signal. The block diagram of a simple PLL is shown in Fig. 1.