Low Power and Improved Read Stability Cache Design in 45nm Technology
نویسندگان
چکیده
–Cache is fastest memory which is played vital role in the present trend.Cache is achieved by SRAM. The scaling of CMOS technology has significant impact on SRAM cell -random fluctuation of electrical characteristics and substantial leakage current. In this paper we proposed dynamic column based power supply 8T SRAM cell to improve the read stability and low leakage. In this paper we compare the proposed SRAM cell with respect to conventional SRAM 6T in read mode. To verify read stability and write ability analysis we use N-curve metric. We extract RC parameters of conventional and proposed SRAM cell in read mode. We proved that proposed system is low power in a memory array.Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, low leakage current and low power in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool. Keywords––Cache, SRAM, Leakage Current, N-curve, Read stability, Write-ability, Cadence, Virtuoso, 45nm Technology.
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Cell Stability Analysis of Conventional 6t Dynamic 8t Sram Cell in 45nm Technology
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