RIG: Targeting Designs with Embedded Memories to ASIC and FPGA Technologies

Design Guidelines for Optimal Results in FPGAs and ASIC Prototypes

Design practices have an enormous impact on an FPGA design’s timing performance, logic utilization, and system reliability. Good design practices also aid in successful design migration between FPGA and ASIC implementations for both prototyping and production. Poor design practices can lead to low performance, high logic or resource utilization, and unstable or unreliable designs associated wit...

Analysis of Resource Utilization in FPGA Implementation of an Embedded System Using Soft Core Processor

Embedded systems are application-specific computers that interact with the physical world. Reconfigurable technologies provide designers the opportunity to diminish the life-cycle in embedded system creation. The basic purpose of using reconfigurable technologies is for solving the problem of obsolescence. New emerging capabilities in Field Programmable Gate Array (FPGA), including improvements...

Position Statements

There was a time – in the dim historical past – when foundries actually made ASICs with only 5000 to 50,000 logic gates. But FPGAs and CPLDs conquered those markets and pushed ASIC silicon toward opportunities with more logic, volume, and speed. Today's largest FPGAs approach the few-million-gate size of a typical ASIC design, and continue to sprout embedded cores, such as CPUs, memories, and i...

Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs

A HIGH−PERFORMANCE MEMORY−EFFICIENT ARCHITECTURE OF THE BIT−PLANE CODER IN JPEG 2000 (ThuAmOR6)

Abstract : The paper presents a high−performance architecture of the bit−plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is dedicated to generate two context−symbol pairs per clock cycle. A novel method called Dynamic Significant State Restoring (DSSR) allows reduction of on−chip memories. The overall design was described in VHD...