A Novel Approach of Vedic Mathematics Using Reversible Logic

This paper is devoted for the design and implementation of a 32bit Arithmetic module it is used for vedic Mathematics algorithms. We have various arithmetic multiplication techniques like Urdhva, Tiryakbhyam, Nikhilam, and Anurupye has been thoroughly analyzed. A 32 x 32 bit multiplier using Urdhava Tiryakbhyam, it has been designed and using this multiplier, a MAC unit has been designed. An Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. We verify these logical modules have been done by using model-sim 65nm. Then the whole design of arithmetic module has been realized on Xilinx Spartan 3E FPGA kit and the product of 32x32 bits is 9.123 ns, and for the MAC operation is 11.151 ns. This paper proposes extension of this 8x8 array multiplication and Urdava multiplication can be implemented by using reversible DKG adder replacing Either Half Adder or Full Adder, by using 16x16-bit, 32x32bit are more than that. Finally this can be dumped in to Xilinx tools in that comparison between the adders like power consumption, and speed.