Scheduling Instructions with Uncertain Latencies in Asynchronous Architectures
نویسندگان
چکیده
This paper addresses the problem of scheduling instructions in micronet-based asynchronous processors (MAP), in which the laten-cies of the instructions are not precisely known. A PTD scheduler is proposed which minimises true dependencies, and results are compared with two list schedulers-the Gibbons and Muchnick scheduler, and a variation of the Balanced scheduler. The PTD scheduler has a lower time complexity and produces better quality schedules than the other two when applied to twenty-three loop-and control-intensive benchmark programs.
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