Optimal output filter design for microprocessor or DSP power supply

Introduction Tight dynamic tolerances for supply voltages of next-generation microprocessors and DSPs at high slew-rate transitions from sleep mode to full-power operation and backwards require fast-transient-response power supplies along with a special decoupling technique. The analysis and optimization of synchronousbuck converters with hysteretic controllers at load-current transients has been presented in References 1 and 2. This article presents a detailed optimization procedure for output filter selection to meet the load-current transient requirements at minimum cost and size. The electrolytic, OS-CON, POSCAP, and ceramic capacitors are compared in a power supply that corresponds to Intel’s VRM 8.4 requirements (see Reference 3). These design examples outline the trade-off between cost, size, and efficiency of the power supply and help the user to choose the optimal solution for any particular application.