The CSYN Verilog Compiler and Other Tools
نویسنده
چکیده
The CSYN Verilog compiler was written by Dr Greaves in early 1994 as a vehicle for research in logic synthesis algorithms and to support experimental extensions to the Verilog language to test highlevel specification techniques. A basic version of CSYN is in use at a number of local companies for industrial FPGA design. This paper describes CSYN and its use with Xilinx devices for teaching. To extend this work, we are defining formal semantics for Verilog, both for simulation and compilation into hardware. This paper reports the performance of CSIM, an X-windows Verilog simulator based on the formal simulation semantics and expresses the desire for a general purpose semantics for Verilog, which can help prove the equivalance of different implementations of a module.
منابع مشابه
Automatic Formal Synthesis of Hardware from Higher Order Logic
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in the HOL4 system, and generates a correctness theorem for each function that is compiled. Logic formulas representing circuits are synthesised in a form suitable for direct translation to Verilog HDL for simulation and i...
متن کاملOverview of the Match Compiler for Compiling Matlab Programs into Hardware
Efficient high-level design tools that can map behavioral descriptions of signal and image processing applications to FPGA architectures are one of the key requirements to fully leverage FPGAs for high-throughput computations and meet time to market pressures. Currently, most FPGA designs are entered at the level of Register Transfer Level (RTL) VHDL or Verilog. It is widely recognized that the...
متن کاملVerification Techniques for COTS Dedication of Commercial FPGA Tools
FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of digital I&C (Instrumentation & Control) in nuclear power plants [1,2]. Commercial FPGA synthesis tools synthesize gate-level designs mechanically from RTL (Register Transistor Logic) designs modeled with HDLs (Hardware Description Languages). Nuclear regulation authorities [3], h...
متن کاملIdentification of non-redundant memorizing elements in VHDL synchronous designs for formal verification tools
Formal tools for the verification of HDL synchronous descriptions are currently in development for both the Verilog [2,3] and VHDL languages [1], but little work has been done on tools able to handle both languages [8]. The well known reason is that VHDL and Verilog's simulation semantics are quite different. So, the task of deciding formally whether two synchronous descriptions written in the ...
متن کاملDevelopment of A Meta Description Language for Software/Hardware Cooperative Design and Verification for Model-Checking Systems
Model-checking tools such as Symbolic Model Verifier (SMV) and NuSMV are available for checking hardware designs. These tools can automatically check the formal legitimacy of a design. However, NuSMV is too low level for describing a complete hardware design. It is therefore necessary to translate the system definition, as designed in a language such as Verilog or VHDL, into a language such as ...
متن کامل