Design of Systolic arrays for QR Decomposition
نویسندگان
چکیده
In this paper we propose design of three systolic arrays to perform QR decomposition of a square matrix. Our first design is based on Given’s rotation method [1]. In contrast to the earlier designs [1], [2] based on this method, our design uses n(n − 1)/2 homogeneous PEs. Our next design is based on Householder method [4]. This method performs only (n− 1) square root operations in contrast to n(n − 1) square root operations performed in Given’s method [6]. Our third design first reduces the given matrix to Hessenberg form [5] and then applies Q-R decomposition to it.
منابع مشابه
Implementation of LU Decomposition and QR Decomposition on Parallel Processing Systems
One of the earliest attempts to implement LU Decomposition with special purpose hardware was using systolic/wavefront arrays[2]. Different proposals for the processing elements(PEs) of systolic/wavefront arrays are provided[3][4][5]. These ideas were not implemented in circuit at that time. The performance of these architectures were not quantitatively evaluated either. In 1994, E. Casseau[6] i...
متن کاملAn inverse QRD-RLS algorithm for linearly constrained minimum variance adaptive filtering
In this paper an inverse QR decomposition based recursive least-squares algorithm for linearly constrained minimum variance filtering is proposed. The proposed algorithm is numerically stable in finite precision environments and is suitable for implementation in systolic arrays or DSP vector architectures. Its performance is illustrated by simulations of a blind receiver for a multicarrier CDMA...
متن کاملA Linearly Constrained IQRD-RLS Algorithm for Blind Multiuser Detection in CDMA Systems
In this paper we propose an inverse QR decomposition based recursive least squares algorithm (IQRD-RLS) for the linearly constrained minimum variance (LCMV) receiver for CDMA transmission systems. The proposed algorithm is numerically stable in finite precision environments and it is suitable for implementation in systolic arrays or DSP vector architectures. It is shown through computer simulat...
متن کاملFault-tolerance and two-level pipelining in VLSI systolic arrays
This paper addresses two important issues in systolic array designs: fault-tolerance and two-level pipelining. The proposed "systolic" fault-tolerant scheme maintains the original data flow pattern by bypassing defective cells with a few registers. As a result, many of the desirable properties of systolic arrays (such as local and regular communication between cells) are preserved. Two-level pi...
متن کاملA hexagonally connected processor array for Jacobi-type matrix algorithms∗
Indexing terms : Parallel algorithms, systolic arrays, matrix computation Jacobi-type matrix algorithms are mostly implemented on orthogonally connected processor arrays. In this letter, an alternative partitioning is described, resulting in a grid of hexagonally connected processors. This partitioning is shown to be over four times more efficient, as compared to the original configuration. Int...
متن کامل