On-chip inductance cons and pros

This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slower CAD tools as compared to RC-based tools. Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty. The viability of design methodologies considering on-chip inductance is briefly discussed. I. HISTORICAL PERSPECTIVE H ISTORICALLY, the gate parasitic impedances have been much larger than the interconnect parasitic impedances since the gate geometries (the width and length) were quite large (about 5 m was a typical minimum feature size in 1980). Thus, interconnect parasitic impedances have historically been neglected and the interconnect was modeled as a short circuit. With the scaling of the minimum gate feature size, interconnect capacitances have become comparable to the gate capacitance, requiring the interconnect to be modeled as a single lumped capacitance that is added to the gate capacitance. With this interconnect model, new design techniques emerged to drive large capacitive loads associated with long global interconnects and large interconnect trees with high fanout. Cascaded tapered buffers are used to minimize the propagation delay of CMOS gates driving these large capacitive loads e.g., [1] and [2]. With increasing device densities per unit area, the cross-sectional area of interconnects has been reduced to provide more interconnect per unit area. Also, the improved yield of CMOS fabrication processes permits manufacturing larger chips with higher reliability. Thus, the global wires connecting modules across an IC have increased in length. Both the decreased cross-sectional area and the increased wire length have caused the global wire resistances to dramatically increase. The interconnect model now includes the resistance of the interconnect. Including resistance in the interconnect model dramatically changed the design and analysis of integrated circuits, e.g., [3]–[5]. With a short circuit or a capacitive interconnect model, the interconnect could be treated as a single node. However, by including the series resistance, the interconnect is composed of multiple nodes, each node having a different voltage waveform. This characteristic has greatly complicated the analysis of circuits with resistive interconnect. Completely new problems and design techniques have emerged due to the transition from a capacitive to an RC model such as RC tree analysis techniques, Manuscript received May 8, 2002; revised May 24, 2002. The author is with the Electrical and Computer Engineering Department, Northwestern University, Evanston, IL 60208 USA. Digital Object Identifier 10.1109/TVLSI.2002.808445 clock skew problems, repeater insertion techniques, power consumption estimation, model order reduction techniques, and IR drops in the power supply, to name a few. Almost every aspect of the design and analysis of integrated circuits was affected by the new interconnect model. This paper briefly discusses the importance, effects, and issues involved in a transition from an RC interconnect model to an RLC model which includes the inductance of the interconnect. This transition has the potential to change all aspects of the design and analysis of integrated circuits in analogy to the transition from a capacitive to an RC interconnect model. However, unlike the transition from a capacitive to an RC model which only resulted into undesirable effects, the increasing inductance effects can have several desirable consequences which are pointed out in the paper. The rest of the paper is organized as follows. The increasing importance of including inductance in current and future technologies is discussed in Section II. The pros of on-chip inductance are discussed in Section III. The cons of on-chip inductance are discussed in Section IV. Finally, conclusions on the viability of design methodologies including on-chip inductance is discussed in Section V. II. IMPORTANCE OF INDUCTANCE IN CURRENT AND FUTURE TECHNOLOGIES On-chip inductance has currently become more important with faster on-chip rise times and wider wires. Wide wires are frequently encountered in clock distribution networks and in upper metal layers. These wires are low resistance lines that can exhibit significant inductive effects. Furthermore, performance requirements are pushing the introduction of new materials such as copper interconnect for low resistance interconnect and new dielectrics to reduce the interconnect capacitance. These technological advances increase the importance of inductance. In the limiting case, the advent of high critical-temperature superconductors has created the possibility of realizing high density, extremely high-speed interconnects for integrated circuits. These superconductive interconnects have zero dc resistance and are highly sensitive to inductance. These interconnects are best modeled as lossless transmission lines. On-chip inductance can cause significant errors in current deep submicron technologies. For example, three sets of AS/X [6] simulation results are presented based on IBM’s most recent technology to illustrate the importance of on-chip self and mutual inductances. The first example is a 4-bit coupled bus (see Table I). The second example is a tree coupled with two lines (see Table II). And the third example is a pair of lines coupled with each other (see Table III). In all three examples simulations are done for three cases. In case I, self and mutual inductances are not included. That is, signal lines are considered as standard 1063-8210/02$17.00 © 2002 IEEE 686 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 6, DECEMBER 2002 TABLE I AS/X SIMULATION OF A 4-BIT BUS TABLE II AS/X SIMULATION OF A COUPLED TREE NETWORK TABLE III AS/X SIMULATION OF A PAIR OF COUPLED LINES RC lines with coupling capacitances only. In case II, self-inductance is included, and lines are considered as RLC lines with coupling capacitance, but no coupling inductance. In case III, both self and mutual inductances are included and lines are considered as RLC lines with coupling capacitance and mutual inductance. Results show that the error due to neglecting inductance can be more than 100% for the delay calculation and 70% in the rise time. What makes these errors even more serious is that neglecting inductance and using an RC model always results in underestimating the propagation delay (e.g., see Fig. 1). Thus, VLSI circuits designed using an RC interconnect model may not satisfy the assigned performance targets despite a worst case analysis being applied in the circuit design process. In general, there are two factors controlling the error between an RC and an RLC model. These two factors are the damping factor of an RLC line and the ratio between the input signal rise time to the time of flight of signals across the line [8]. The damping factor of an RLC line is given by