A complete phase-locked loop power consumption model - Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/5% of the power consumed at the final frequency) is incurred during the acquisition process. 1. The PLL dynamic behavior The PLL can be described as a 2 order continuous time system. For a step of magnitude Astep in the input frequency, the time response is given by: ( ) [ ] ) ( sin 1 cos ) / 1 ( 1 ) ( 1 2 n n t d step o t e N A t f n ξω + ξ − ω ω − = − ξω − CN I K C I K N R CH V n CH V =       = ω ξ ; 1 2 If the frequency step takes the VCO frequency beyond the lock range, then a capture (pull-in) process takes place initially. Otherwise, only a lock process occurs, which is defined by tlock. These times can be expressed as: CH V o capture o capture n lock I K C f t f t t 2 ) 0 ( ) ( ; 1 − = ≈ ξω For the VCO gain KV (Hz/V), we need to calculate: