Efficient Hybrid Method for Binary Floating Point Multiplication

This paper presents a high speed binary floating point multiplier based on Hybrid Method. To improve speed multiplication of mantissa is done using Hybrid method replacing existing multipliers like Carry Save Multiplier, Dadda Multiplier and Modified Booth Multiplier. Hybrid method is a combination of Dadda Multiplier and Modified Radix-8 Booth Multiplier. The design achieves high speed with maximum frequency of 555 MHz compared to existing floating point multipliers. The multiplier implemented in Verilog HDL and analyzed in Quartus II 10.0 version. Hybrid Multiplier is compared with existing multipliers. Keywords— Hybrid method, Dadda Multiplier, Booth Multiplier, Floating point multiplication, Verilog HDL;