On the Reliability of an InGaZnO Thin-Film Transistor under Negative Bias Illumination Stress
نویسندگان
چکیده
The positive gate-bias temperature stress (PBTS)-induced instability in top gate self-aligned coplanar InGaZnO thin-film transistors is experimentally decomposed into contributions of distinct mechanisms by combining the stress-time-divided measurements and the extraction of subgap density-of-states (DOS) from the optical response of C-V characteristics. It is found that a total threshold voltage shift (DVT,tot) under PBTS is decomposed into three mechanisms: 1) increase of DOS due to excess oxygen in the active region (DVT,DOS), 2) shallow (DVT,shallow) and 3) deep charge trapping in the gate insulator components (DVT,deep). All DVT components are well fitted with the stretched-exponential (SE) functions with individual parameters and the DVT,tot(t) is well described by the superposition of multiple SE functions. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for joint optimization of the dielectrics, the active layer, and the interfaces towards ultimate PBTS stability.
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