Real { Time Mpeg { 2 Software
نویسندگان
چکیده
{ A single chip system for real{time MPEG{2 decoding can be created by integrating a dual{issue RISC processor with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 16KB data RAM. The VLD hardware performs the Huuman decoding on the input data. The block loader performs the half{sample prediction for motion compensation and acts as a direct memory access controller for the RISC processor. The dual{issue RISC processor, running at 250MHz, is enhanced with a set of key sub{word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG{2 decoding applications, bi{directionally predicted non{intra blocks are decoded in less than 800 cycles, leading to a single chip, real{time MPEG{2 decoding system.
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