Architecture and Design of Shared Memory Multi- QueueCore Processor

The multi-core systems have been proposed because a processor performance cannot be achieved by simply increasing clock frequency. The issues of synchronization mechanisms and memory arbitration are very important in constructing the multi-core system. We implemented the Bus Arbitration to control the memory accesses in a multi-core system. All processor cores in the system are connected via a shared bus and communicate using the shared memory. The number of the memory accesses affects improving performance in our shared memory multi-queue core system. In this thesis, we discuss a design of Bus Arbitrator Mechanism and performance results.