Analysis of the Performance of Coarse-Grain Reconfigurable Architectures with Different Processing Element Configurations

Several coarse-grain reconfigurable architectures have been proposed in recent years that consist of a large number of processing elements connected together in a network. These architectures vary widely from each other – particularly, the processing elements (PEs) in these architectures range from simple functional units to entire RISC cores and micro-controllers. In this paper, we study the effect of different PE architectures on the quality of results (performance) of mapping applications to coarse-grain architectures. We present a scheduling and mapping heuristic that takes the interconnections between PEs and the delays on these interconnections into consideration while mapping applications to the PEs of mesh-like coarse-grain architectures. We perform experiments in which we vary the number of functional units in the PEs, the functionality of these units, the number of PEs in the architecture, and the delays on the interconnect that connects the PEs. Our results for a set of designs derived from DSP applications demonstrate that larger grids do not necessarily translate into better performance. Often, there is not enough instruction-level parallelism (ILP) in the designs to fully utilize the PEs in the fabric. Also, our results show that increasing either the number of functional units in each PE or the interconnections among PEs leads to much better quality of results.