Optimizing Programmable Logic Arrays Using the Simulated Annealing Algorithm
نویسندگان
چکیده
In the paper the programmable logic array (PLA) topological optimization problem is dealt with using folding techniques. A PLA folding algorithm based on the method of simulated annealing is presented. A simulated-annealing PLA folding algorithm is presented for multiple unconstrained folding. Then, the algorithm is extended to handle constrained folding. In this way, simple folding is considered as a case of multiple constrained folding. Some experimental results of computer investigation of the suggested algorithms are given.
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