Testing of N-Stage 1 bit per stage Pipelined ADC using Test Input Regeneration

Analog-to-Digital Converters (ADCs) became an integral part in most systems. The Pipelined ADC (PADC) is one of the preferred ADCs; it is perfect for applications requiring high speed and medium resolution. Hence, the test of ADCs in general as well as PADCs is not only interesting but mandatory; the need for a low cost and efficient test technique in order to test the PADC is increasing. The focus in this paper is on proposing a new efficient test technique fitting an N-stage PADC test. The proposed technique depends on the selection of test inputs that can be applied to the first stage of the PADC and it is guaranteed that they can be regenerated at the input of next stages in the PADC. This proposed technique does not use complex hardware and there is no need to access the input or output of each individual stage. It will be shown that only two DC test inputs are able to detect all catastrophic faults in the N-stage PADC producing 100% fault coverage. The simulation results are based on circuit-level simulations using the Eldo simulator provided by Mentor Graphics. Key-Words: PADC, Test Input Regeneration, N-stage, Catastrophic, Fault model, Structural test.