Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1.5 V supply voltage, 20 MHz clock frequency, and less than 0.1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential ampli®er so that the feed through errors from switches cancel out. The MOS current mode S/H circuit is designed and simulated using CMOS 0.6 mm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0.1%, and 1 MHz input from a 1.5 V power supply is achievable.