Timing Analysis of Quasi-Delay-Insensitive Ripple Carry Adders – A Mathematical Study
نویسندگان
چکیده
This paper deals with the timing analysis of quasi-delay-insensitive (QDI) ripple carry adders from a mathematical perspective. In this context, this paper throws light on forward latency, backward latency and cycle time metrics of robust asynchronous adders, which correspond to either strong or weak-indication timing regimes. With respect to weak-indication, both distributive and biased design approaches are considered. The analysis shows that the biased implementation style is preferable for realizing QDI carry-ripple adders of arbitrary size, and the mathematical results derived are independent of technology and logical composition. Key-Words:Self-timed design, QDI, Indication, Latency, Cycle time, Ripple carry adder.
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